The present invention relates generally to semiconductor device fabrication. More specifically, the present invention relates to methods of making self-aligned contacts for salicided MOS devices.
Self-aligned contacts (SACs) are used in many semiconductor technologies such as DRAMs, SRAMs, and Flash memory. Conventionally, tungsten silicide (WSi.sub.x) has been used as polycide (preformed and deposited silicide) and diffusions have not been silicided. In such cases, self-aligned contacts can be implemented using a polysilicon gate stack (e.g., poly 1/tungsten silicide (WSi.sub.x)/silicon oxynitride (SiON)) because the SAC mask etch can selectively stop on SiON and diffusion materials while etching oxide.
A semiconductor device having a conventionally formed SAC is illustrated in FIG. 1. The device 100 is formed on a semiconductor substrate 102, typically composed of monocrystalline silicon. The device 100 is formed according to a series of fabrication steps well known to those of skill in the art. First, isolation regions (not shown) are formed on the substrate 102. Then a gate oxide layer 104 is formed on the surface of the substrate 102.
Next, a layer of polysilicon is formed on the gate oxide layer, typically by using a chemical vapor deposition (CVD) process well known to those with skill in the art. This polysilicon deposition step is followed by deposition of two additional layers of material, also typically using CVD. The first of these layers is composed of tungsten silicide (WSi.sub.x), which collectively with the polysilicon layer is referred to as a "polycide" when the tungsten silicide deposited in this manner. The second layer is of a dielectric material that is resistant to a self-aligned contact etching procedure to be subsequently applied. Typical examples of this material include silicon oxynitride (SiON) or silicon nitride (Si.sub.3 N.sub.4).
This three-layer stack is then patterned and etched to form distinct gates. The etch chemistry should have good selectivity to oxide so that the gate oxide material exposed by the etch on either side of the gates prevents penetration into the substrate. A typical etch may include two steps: a first step using chemistry to etch the top silicon oxynitride or silicon nitride layer. And the second step using chemistry to etch the silicide and polysilicon layers and stop at the gate oxide layer 104. In the example shown in FIG. 1, two gates are formed by the gate layer stack etch. Each gate is composed of a polysilicon layer 106, a tungsten silicide layer 108, and a SAC etch stop layer 110.
Once the gates have been formed, an LDD implant is performed to produce a shallow diffusion region 112 at the surface of the substrate 102 between and beside the gates. Then, sidewall spacers 114 are formed in a conventional manner by deposition of an oxide (TEOS), oxynitride, or nitride layer followed by an anisotropic etch. Deep implants 116 are then formed according to conventional procedures.
Following formation of the sidewall spacers 114 and diffusion regions 112/116, an interlayer dielectric 118 is formed. The second layer of dielectric 118, typically oxide (TEOS), is patterned and etched to form a contact hole. This etch step is referred to as a self-aligned contact etch because the SAC etch stop layer 110 and sidewall spacer 114 are not removed by the etch chemistry. The resulting physical contact area is self-aligned to the gate stacks, and does not require alignment of the contact to the gates. The SAC etch chemistry is selected to remove the oxide material of layers 118 and 104, while stopping on the silicon and silicon oxynitride or silicon nitride of the SAC etch stop layer 110, and minimally etching sidewall spacers 114.
Once the SAC etch has formed the contact hole, a layer of interconnect material 120 is deposited, patterned and etched to form a contact between the diffusion area 112/116 and a conductor above it (the conductor is not shown in FIG. 1).
This conventional process and structure has several drawbacks. First of all, the diffusion sheet resistance is relatively high since the diffusion is not silicided. Secondly, stress in tungsten silicide can be high, so that when gate oxide is scaled down below about 50 .ANG., reliability problems are experienced. In addition, tungsten silicide has a relatively high resistance for a silicide material, especially when line widths are scaled down.
In order to address these problems, titanium salicide (self-aligned titanium silicide) may be used. However, since substitution of a titanium salicide process into the conventional process would result in diffusions and polysilicon gates which are silicided after gate patterning and spacer processing, there would be no SAC etch stop layer present in the gate stack. Thus, the contact's interconnect material would short the gates to the diffusion following SAC processing.
Accordingly, what is needed is a method for self-aligned contact processing that provides improved reliability and decreased sheet resistance as semiconductor device sizes are decreased, and does not produce the drawbacks discussed above.